Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Role Overview

Astera Labs is seeking a hands-on Principal DFT Engineer to drive DFT architecture and execution for its signal-conditioning products that enable high-speed connectivity in rack-scale AI infrastructure. This is an individual-contributor role focused on technical ownership and delivery.

The role can expand into a people-management path for the right candidate. We are advertising at the Principal individual-contributor level and remain open to discussing a management track where it is a strong fit.

You will own day-to-day DFT work while partnering with design, verification, physical design, packaging, product engineering, and manufacturing teams. The focus is advanced multi-die designs, with emphasis on test coverage, diagnostics, yield, and production readiness for high-speed PCIe and Ethernet products. You will diagnose complex DFT integration and tool-related issues, reason through unfamiliar problems, and help the Toronto team build capability for future multi-die programs.

Key Responsibilities

Define and drive DFT plans for signal-conditioning products supporting high-speed connectivity and advanced multi-die packaging.
Develop test-access, coverage, observability, and diagnostic strategies for die-to-die interfaces, interposers, and package-level integration.
Lead implementation and verification of scan, ATPG, compression, memory BIST, boundary scan, and related DFT features while balancing area, timing, routing, and manufacturability.
Work with Design, STA and Physical Design teams to accurately craft constraints, placement and design structures needed to implement DFT
Set coverage targets, review ATPG results and pattern quality, and influence test-time and production economics.
Support tape-out, wafer sort, packaged-device test, silicon bring-up, characterization, and production ramp.
Collaborate with product, manufacturing, assembly, and test teams on yield learning, failure analysis, and root-cause resolution.
Build pre-bond, post-bond, and package-level test approaches that enable known-good-die screening.
Diagnose DFT integration and tool-related failures and resolve issues cross-functionally.
Mentor engineers and contribute to building DFT capabilities in the team.
Partner with OSATs, ATE vendors, packaging partners, and internal stakeholders; communicate risks and trade-offs clearly.

Required Qualifications

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
Minimum 8 years of relevant DFT or semiconductor design-and-test experience.
Demonstrated expertise in boundary scan, memory BIST (MBIST), and automatic test pattern generation (ATPG).
Hands-on experience with DFT/EDA tools for test insertion, pattern generation, verification, or diagnostics.
Solid understanding of the ASIC design flow, from RTL through GDS and DFT signoff.
Working knowledge of 2.5D/3D packaging techniques, backside bus implications for test and diagnosis, and DFT methodologies for 3D designs.
Strong analytical and problem-solving skills, with the ability to independently troubleshoot unfamiliar DFT integration and tool-related challenges.
Familiarity with high-speed interface or advanced packaging test concepts.

Preferred Qualifications

Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related field.